4 ms·
For the power-efficiency, in-order superscalars proved to be efficient enough - see various in-order superscalar ARMs. Even for OOO, various ARMs and Apple show
by drivebycomment 6y ago
For the power-efficiency, in-order superscalars proved to be efficient enough - see various in-order superscalar ARMs. Even for OOO, various ARMs and Apple showed that they can get quite power efficient.
Also, more importantly, VLIW is not a power efficient approach. It fundamentally wastes instruction density. It wastes the die space - superscalar + SMT are inherently more efficient when you have more than 1 thread, and VLIW is suboptimal for SMT. It also turns out in-order superscalars can match VLIW in ALU power efficiency by powering off unused ALUs just like VLIW can, and for applications where the power efficiency is more important, the control logic can be simplified enough (at the price of performance obviously) to add negligible power overhead.
As for the security aspect of the speculative execution, OOO outperforms VLIW dramatically for a single thread performance even without any speculative execution. Moreover, since the discovery of Spectre, there's been plenty of research into how to do speculative execution without leaking:
https://ieeexplore.ieee.org/abstract/document/8806916 https://ieeexplore.ieee.org/abstract/document/8806916
https://ieeexplore.ieee.org/abstract/document/8574559 https://ieeexplore.ieee.org/abstract/document/8574559
https://ieeexplore.ieee.org/abstract/document/9138957 https://ieeexplore.ieee.org/abstract/document/9138957
https://dl.acm.org/doi/abs/10.1145/3316781.3317914 https://dl.acm.org/doi/abs/10.1145/3316781.3317914
It's not yet clear what approach will actually win out and will be adopted, but it's clear there are multiple viable solutions such that this is a solvable problem. The whackamole of fixing / addressing individual spectre-like vulnerability likely will continue for a while - after all, processor folks didn't have that much time given the development cycle for new pipeline/architecture is measured in years - but it's unlikely that side-channel issue will make speculative execution not viable.
Edit: s/SIMT/SMT/
- zozbot234 6y ago> It fundamentally wastes instruction density It would seem that instruction compression can be used to recover that density in many cases. Even Itanium did something like that IIRC, and of course the Mill is noticeably reliant on cheap representation of "unused" instructions. > It wastes the die space - superscalar + SIMT are inherently more efficient when you have more than 1 thread I don't believe this at all. SIMT encompasses approaches such as barrel processing, and wide-SIMD plus predication as an alternative to branching code, that while effective in some specialized cases are hardly "inherently" preferable in general.
- drivebycomment 6y agoI meant to put SMT not SIMT.