4 ms·
x86 has a quite variable instruction size, up to 15 bytes. So an x86 decoder will be more complicated than an ARM or RISC-V decoder. I'm pretty sure that means
by nsajko 6y ago
x86 has a quite variable instruction size, up to 15 bytes. So an x86 decoder will be more complicated than an ARM or RISC-V decoder. I'm pretty sure that means that designing performant IP is more difficult engineering-wise for x86.
- ncmncm 6y agoNo doubt, but it is already worked out. And it turns out to take up a remarkably small area of the die. So, unless it actually slows down execution, it is a small tax that is overwhelmed by benefits of volume production.