But I can tell you from working in the industry that RISC-V is already competitive with ARM in some segments. You're spot on with your analysis, but I don't thi

But I can tell you from working in the industry that RISC-V is already competitive with ARM in some segments. You're spot on with your analysis, but I don't think you understand that for some designs, the CPU and the software are developed and verified in tandem. If your design works with the firmware you intend to run on it in simulation, it's very likely to work in hardware as well. This is why you see RISC-V adopted in things like hard drive controllers and such first. You're starting to see RISC-V used more and more in internal processors that's never going to be programmed by a third party. This also means you'll see more and more vendors of RISC-V cores and RISC-V verification suits. Chip designers are just as willing to pay a license and support fee to these as to ARM, as long as the cost is lower. So I'm absolutely certain that you'll eventually see RISC-V cores verified to the same level as ARM. Also remember that open source RISC-V cores is more likely to get free verification efforts from universities, students and hobbyists. > The only way for an open source chip design to be remotely competitive would be if they were to embrace FPGA technology. But FPGAs run 4 times slower than purpose built ASICs and are at least 10 times more expensive per unit in volume. Ah, yes, but you can verify on FPGA and ship on ASIC. That's why even hobbyists can now work on developing and verifying RISC-V cores. These days it's really not that hard to verify a microcontroller-level CPU core. It might take a long while until you get a state-of-the-art superscalar multicore RISC-V CPU for servers and desktops, but I think it'll eventually happen for RISC-V the same way it did for ARM. Hell, the open-source designs are already there, and they're pretty well verified, which is way further than ARM was at the same stage (they had zero incentives to do anything that wasn't commercially viable after all, unlike the research communities developing RISC-V cores), you just need further optimization and verification.