3 ms·
"As the experience of realtime audio illuminates, it’s hard enough scheduling CPU tasks to reliably complete before timing deadlines, and it seems like GPUs are
by guhcampos 6y ago
"As the experience of realtime audio illuminates, it’s hard enough scheduling CPU tasks to reliably complete before timing deadlines, and it seems like GPUs are even harder to schedule with timing guarantees."
Well, I suppose that's way more feasible in RISC CPUs.
Damn I hate when Apple is right about something.
- monocasa 6y agoRISC as a concept doesn't really help you with making timing guarantees.
- est31 6y agoYeah as of today, the instruction language used isn't really relevant anyway. You still have to figure out the same problems as a chip designer.
- danhor 6y agoMore modern/better arm cores and common environments (starting at approx. Cortex-M3 microcontrollers, where flash instruction fetching depends on page alignment) are also pretty unpredictable. In fact, most advanced pipeline designs, no matter the ISA, have very hard-to-predict instruction timings. Couple this with dynamic frequency scaling and the instruction timings are irrelevant.