Thanks for the perspective and GMPbench reference. I'm sure you're correct that RISC-V has a lot of optimization work to do both at the compiler and chip imple

Thanks for the perspective and GMPbench reference. I'm sure you're correct that RISC-V has a lot of optimization work to do both at the compiler and chip implementation levels. I'm curious whether vector operation support in RISC-V might also make up for any apparent shortcomings in raw arithmetic throughput - I guess a lot of it will depend on the types of workloads involved.