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I am actually pretty curious to see a demo of features from you that backs up that RISC-V is bad and Open Power is much better. What convinced me was how thin
by robot 6y ago
I am actually pretty curious to see a demo of features from you that backs up that RISC-V is bad and Open Power is much better.
What convinced me was how thin the RISC-V book[1] is, and I have seen both ARM and Intel reference manuals. For example the V extension removes need to specify data size, greatly reducing instructions needed.
I have no idea about Open Power btw.
[1] http://riscvbook.com/ http://riscvbook.com/
P.S. I am hiring U.S. candidates for ARMv8, x86 roles: https://careers.vmware.com/main/jobs/R2009422?lang=en-us https://careers.vmware.com/main/jobs/R2009422?lang=en-us
- saagarjha 6y agoWhile I’m not really an expert on either, I have looked at code for both and I got the impression that RISC-V’s “simplicity” is actively harmful to making it a good ISA outside of teaching because it’s instructions are just not really all that great; indexing into an integer array (for example) is a shift, add, then load while basically every other architecture can do this in one instruction. It seems to me that the ISA is really designed more towards being pretty than being practical.