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>I cant wait to see a SSD Controller with this tech I doubt this will improve SSD controllers, whilst this may have more granular control over the CPU cache.
by Zenst 6y ago
>I cant wait to see a SSD Controller with this tech
I doubt this will improve SSD controllers, whilst this may have more granular control over the CPU cache. For example - if there was an SSD controller that this was drop-in compatible, I doubt there would be any measurable gains due to the NAND latency and that if your a little late, the NAND isn't going anywhere.
Spinning rust, now if you miss the rotation, you have to wait a full rotation. However, given rotation speeds, the processing has been fine as and the days of interleaving sectors to time the controller performance died out decades ago, so I'm not sure that example would see gains.
Remember that in these cases the code is kinda fixed and the only dynamic is streaming the data in or out and processing upon that data (encoding/decoding) - all fixed. So if the core/cache is fixed upon one task, the whole latency aspect is controlled and known. However, if you want a CPU to do many things, then this level of cache control and interrupt handling would be more important, so then you need an RTOS.
Though I'm sure many a dB would love the ability to run code directly upon the drive controller - then with RTX30 opening up direct drive interfacing over the bus and circumnavigating the CPU[EDIT]- then again, this may well have some advantages.
[EDIT ADD] Easier access to large ram caches seems to be the real gain, so for spinning rust HD's, that becomes a mixed blessing as would ideally want some capacitors to make sure that memory buffer is written in case of a power failure - so more memory buffer, large capacitors to make sure enough power to flush that buffer to the spinning rust. So be interesting how that pans out.
- jasonwatkinspdx 6y agoThe FTL layer in modern SSDs is far more complex than you're describing above. It's not about NAND latency, it's about having good enough scheduling and enough raw throughput on checksumming and such to match the ever increasing stacks of NAND and consequent bandwidths.