> in what ways is the design of microcode instruction-sets for CISC-ISA CPUs, different from the design of outward-presenting RISC ISAs? There's a lot of varia

> in what ways is the design of microcode instruction-sets for CISC-ISA CPUs, different from the design of outward-presenting RISC ISAs? There's a lot of variability in microcode designs, but based on the microcodes I've examined closely (various IBM 360 mainframes, Xerox Alto, 8086), there are several characteristics. Microcode is usually much wider than instructions (21 bits for the 8086, over 100 bits for some IBM machines). Microcode is usually doing several things in parallel. An instruction set is designed to be general-purpose and "make sense", while microcode is nearly incomprehensible and does whatever bizarre tricks are necessary to implement just what is needed for the instruction set. (One important factor is that microcode doesn't need to be backwards or forwards compatible, so designers can do whatever they want.) Microcode's relationship with memory is different since you're dealing with address and data registers, not abstract reading and writing of memory. Microcode needs to worry a lot more about timing. For instance, in the 8086, an ALU operation is set up a cycle before it happens. In the Xerox Alto, conditional branches happen a cycle after you issue them. For your specific question about registers, much of the 8086's microcode ignores the specific register names, saying things like move the generic source register to the ALU. The hardware selects the appropriate register based on the instruction, direction bit, etc. (I'm in the middle of writing a blog post about this.) For a more modern look at microcode, the book "The Anatomy of a High-Performance Microprocessor" describes the AMD K6 processor in way more detail than you'd want.