So go to the 6502 for an example which has a decode ROM which is similar in concept, but far more primitive and fixed rather than programmable.. Instructions t

So go to the 6502 for an example which has a decode ROM which is similar in concept, but far more primitive and fixed rather than programmable.. Instructions take a length of time from 2 to 7 cycles, with an additional cycle under certain conditions. The decode ROM determines what is done for each of those cycles and allow the modularization of circuity for common purposes among instructions. I think CPUs such as the Z80 and definitely the 68000 had more sophisticated mechanisms where the microcode was really a sub-CPU executing actual micro-instructions. > I've also been curious whether there are any lessons in the design of microcode ISAs, that can be applied in the design of abstract-machine bytecode ISAs. I think something like Itanium's VLIW breaks this barrier between microcode and ISA more than other ISAs and the lesson was it's too difficult to port legacy software to it, so we keep going on with CPUs that continue to support the appearance of an in-order ISA initially developed in the 1970's with more and more frankensteined extensions as time goes on.