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In my experience, CISC instruction sets are primarily a way to create compact representations of fairly long instruction words. That arises from the way in whi
by ChuckMcM 6y ago
In my experience, CISC instruction sets are primarily a way to create compact representations of fairly long instruction words.
That arises from the way in which the register file, the ALU, the flags, and various counters (instruction, stack, Etc) are laid out in logic and the buses between them.
Something that I find really fun to do is to experiment with compute architectures. I first started playing around with this with an Altera DE2 board, then the Spartan III dev board from Xilinx, and these days with a Lattice Ice40K board (Icebreaker, and soon ULX3S board). There are a number of "soft" CPUs where you can play around with this to your hearts content (given you have enough gates in your FPGA, which is getting easier and easier these days).
CISC instructions are, as the name suggests, are simply "subroutine calls" or "macro calls" (depending you what era of computing you were introduced to) into an underlying machine that can move bits around each "clock". RISC is essentially making that level of instruction available directly to the compiler.
The most infamous version of exposing what is essentially microcode to the compiler was, in my opinion, the Itanium which has a really flexible native instruction set that the compiler mixed and matched into pseudo instructions which it used to compile code into. A more elegant version of this was the Xerox PARC "D" machines which allowed you to load an instruction set prior to booting into your actual applications. This made Mesa[1] development interesting because you needed the appropriate instruction set to go with the Mesa compiler you were using.
[1] Mesa was Xerox's modular development language that inspired Wirth's Modula 2 (I believe that was the ordering, Wirth might claim it went the other way)
- bogomipz 6y ago>" There are a number of "soft" CPUs where you can play around with this to your hearts content (given you have enough gates in your FPGA, which is getting easier and easier these days)." Could you make some recommendations for a newcomer in terms of ease of use and good tooling? Thanks.
- ChuckMcM 6y agoPerhaps the easiest way to get set up is to get a ULX3S from Crowd Supply[1], and then download the "official" tool chain from Github[2]. This project[3] is a good hackable target. There are interesting examples for this board here[4]. A better collection of links are here: https://ulx3s.github.io/ https://ulx3s.github.io/ You'll need to develop some HDL skills (which is a deep dive) but it is well worth it to make experimental computer architectures! [1] https://www.crowdsupply.com/radiona/ulx3s https://www.crowdsupply.com/radiona/ulx3s [2] https://github.com/ulx3s/ulx3s-toolchain https://github.com/ulx3s/ulx3s-toolchain [3] https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radiona/ulx3s/smp https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radio... [4] https://github.com/emard/ulx3s-examples https://github.com/emard/ulx3s-examples
- bogomipz 6y agoThanks for the recommendation this is a great list of links. You states: >"You'll need to develop some HDL skills ..." Do you have some of recommendations on where to begin with that? Thanks
- ChuckMcM 6y agoWell there are two popular HDLs, one is Verilog and the other VHDL. In my experience Verilog is more popular both in github repositories and around the industry, so you could get something like "Verilog by Example"[1] which is a pretty concise jump into building things with Verilog. There are a number of universities that put their Verilog course notes on-line and that is a good source of reference material as well. [1] https://www.amazon.com/Verilog-Example-Concise-Introduction-Design/dp/0983497303 https://www.amazon.com/Verilog-Example-Concise-Introduction-...