Thanks. As always, context is everything and this is certainly more than was implied by the blurb. Hopefully we can rest it here. The fundamental chase of ba

Thanks. As always, context is everything and this is certainly more than was implied by the blurb. Hopefully we can rest it here. The fundamental chase of bandwidth-per-pin hasn't stopped. Two recent examples: Eton RPC DRAM manages to essentially run the whole protocol over the data wires using just 22 pins for a 16-bit DDR bus. Another: GDDR6X finally introduced PAM4 (four voltage levels per pin = double the bandwidth). Now we just need to combine these ideas ...