4 ms·

Aren't you mixing two things? TRISTATE was required to hook up multiple chips _data_ lines, yes, but not the address lines, which are input-only. If the innov

Aren't you mixing two things? TRISTATE was required to hook up multiple chips _data_ lines, yes, but not the address lines, which are input-only. If the innovation was sharing the data bus, then, sure, that would make more sense. FWIW, even the 4004 (1971, predating the MK4096 by three years) used multiplexing and I'm sure it was a known approach prior to that.

dragontamer 6y ago
> Aren't you mixing two things? TRISTATE was required to hook up multiple chips _data_ lines, yes, but not the address lines, which are input-only. If the innovation was sharing the data bus, then, sure, that would make more sense. You're right in this instance. ------------ The innovation therefore, was coming out with a 16-pin RAM chip when everyone else was coming out with 22-pin RAM chips. Looking up the history of the time, Intel, and other big companies, were betting on 22-pin RAM chips to deal with the addressing issue. The innovation was realizing that you're strobing RAS (Row Address) and CAS (Column Address) in separate cycles anyway. By using those separate cycles, you only needed 6-pins to address, even on bog-standard address busses. Sure, the Intel chip may have a 16-bit address bus, but the MK4096 didn't care. Wire up the bottom 12-bits, 2-pins to each input address pin, and you're set. Seems brilliant to me. ------- I keep looking at the datasheet and the main thing that annoys me is that its wasteful TTL. But I guess that was the late 60s / early 70s for ya, CMOS wasn't invented yet so I guess TTL was what they used.
- FullyFunctional 6y ago
  Thanks. As always, context is everything and this is certainly more than was implied by the blurb. Hopefully we can rest it here. The fundamental chase of bandwidth-per-pin hasn't stopped. Two recent examples: Eton RPC DRAM manages to essentially run the whole protocol over the data wires using just 22 pins for a 16-bit DDR bus. Another: GDDR6X finally introduced PAM4 (four voltage levels per pin = double the bandwidth). Now we just need to combine these ideas ...

dragontamer 6y ago

> Aren't you mixing two things? TRISTATE was required to hook up multiple chips _data_ lines, yes, but not the address lines, which are input-only. If the innovation was sharing the data bus, then, sure, that would make more sense. You're right in this instance. ------------ The innovation therefore, was coming out with a 16-pin RAM chip when everyone else was coming out with 22-pin RAM chips. Looking up the history of the time, Intel, and other big companies, were betting on 22-pin RAM chips to deal with the addressing issue. The innovation was realizing that you're strobing RAS (Row Address) and CAS (Column Address) in separate cycles anyway. By using those separate cycles, you only needed 6-pins to address, even on bog-standard address busses. Sure, the Intel chip may have a 16-bit address bus, but the MK4096 didn't care. Wire up the bottom 12-bits, 2-pins to each input address pin, and you're set. Seems brilliant to me. ------- I keep looking at the datasheet and the main thing that annoys me is that its wasteful TTL. But I guess that was the late 60s / early 70s for ya, CMOS wasn't invented yet so I guess TTL was what they used.

FullyFunctional 6y ago
Thanks. As always, context is everything and this is certainly more than was implied by the blurb. Hopefully we can rest it here. The fundamental chase of bandwidth-per-pin hasn't stopped. Two recent examples: Eton RPC DRAM manages to essentially run the whole protocol over the data wires using just 22 pins for a 16-bit DDR bus. Another: GDDR6X finally introduced PAM4 (four voltage levels per pin = double the bandwidth). Now we just need to combine these ideas ...