> You have RISC-V chipping away the bottom, low end embedded category... Yes. For relatively simple in-order cores, the RV32 instruction set is far simpler to

> You have RISC-V chipping away the bottom, low end embedded category... Yes. For relatively simple in-order cores, the RV32 instruction set is far simpler to implement than ARM, or even MIPS, and should be able to provide better performance. If the existing SW dev toolchain is sufficient for your needs right now, I think RISC-V can be a great choice for small embedded SoCs.