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I'm talking about this image: https://images.anandtech.com/doci/16063/474551355-Intel-Blueprint-Series-11th-Gen-Intel-Core-Processors-pdf-page-034.jpg https://

by 3JPLW 6y ago

I'm talking about this image: https://images.anandtech.com/doci/16063/474551355-Intel-Blueprint-Series-11th-Gen-Intel-Core-Processors-pdf-page-034.jpg https://images.anandtech.com/doci/16063/474551355-Intel-Blue... I don't see any coherent fabric blocks — what looks like large cache sections to my eyes are entirely inside the "Core" blocks. Maybe they're just not drawn correctly. Here are some much older i7s, for example: https://www.cs.uaf.edu/2009/fall/cs441/proj1/russell/images/df94g6m6_4gxrw53gk_b.png https://www.cs.uaf.edu/2009/fall/cs441/proj1/russell/images/... https://www.notebookcheck.net/fileadmin/_migrated/pics/Core_I7_LGA_2011_Die-1.jpg https://www.notebookcheck.net/fileadmin/_migrated/pics/Core_...

wmf 6y ago
The labeling on that image is... approximate. You can see the orange L3 blocks inside the area labeled as cores and it's still shared.
- 3JPLW 6y ago
  > it's still shared Right, that was really my main question: besides the labeling (which is of course approximate), the positioning sure looks like each core would have its own "favorite" section of the cache. And being shared, it seems like this could make for some interesting performance behaviors. Ah, interesting, this topology was introduced with Sandy Bridge. I'm just out of date: https://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/4 https://www.anandtech.com/show/3922/intels-sandy-bridge-arch...
  - icegreentea2 6y ago
    Yeah, you need something like that to scale to large core counts, and especially if you wanna pull off some chiplet goodness (like AMD did with Ryzen). I think that's why it got lumped with the Fabric Interconnect layer in one of the block diagrams.
icegreentea2 6y ago
I found another annotated shot of your anandtech shot: https://cdn.wccftech.com/wp-content/uploads/2020/08/Intel-Tiger-Lake-11th-Gen-Mobile-CPU-10nm-Die-Shot_2.jpg https://cdn.wccftech.com/wp-content/uploads/2020/08/Intel-Ti... Looks like ya, the L3 cache is "inside" the core blocks.

by 3JPLW 6y ago

wmf 6y ago

The labeling on that image is... approximate. You can see the orange L3 blocks inside the area labeled as cores and it's still shared.

3JPLW 6y ago
> it's still shared Right, that was really my main question: besides the labeling (which is of course approximate), the positioning sure looks like each core would have its own "favorite" section of the cache. And being shared, it seems like this could make for some interesting performance behaviors. Ah, interesting, this topology was introduced with Sandy Bridge. I'm just out of date: https://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/4 https://www.anandtech.com/show/3922/intels-sandy-bridge-arch...
- icegreentea2 6y ago
  Yeah, you need something like that to scale to large core counts, and especially if you wanna pull off some chiplet goodness (like AMD did with Ryzen). I think that's why it got lumped with the Fabric Interconnect layer in one of the block diagrams.

icegreentea2 6y ago

I found another annotated shot of your anandtech shot: https://cdn.wccftech.com/wp-content/uploads/2020/08/Intel-Tiger-Lake-11th-Gen-Mobile-CPU-10nm-Die-Shot_2.jpg https://cdn.wccftech.com/wp-content/uploads/2020/08/Intel-Ti... Looks like ya, the L3 cache is "inside" the core blocks.