3 ms·
It's easy to write that program. For example, a Peterson lock, which has a busy-wait loop: while (flag1 == true && turn == 1) { /* wait */ } the loop term
by millstone 6y ago
It's easy to write that program. For example, a Peterson lock, which has a busy-wait loop:
while (flag1 == true && turn == 1) { /* wait */ }
the loop terminates by another thread writing to either variable.
If the variables were mirrored to registers, and that mirroring was not invalidated by another thread's write, then the loop would never terminate.
Of course Zen2 did not break Peterson locks, so the GP's question is cogent and has the answer "yes, there is such logic."
- deleted 6y ago[deleted]
- deleted 6y ago[deleted]
- chrisseaton 6y agoBut the read of turn will not be eternally mirrored to the original write - at some point the rename file eventually moves on when the original store (an observable side effect) retires like a register renaming. Notice that your code has a backward jump between the write and the read and the example in the article (and the code of the other person I replied to) does not. There is no logic needed to interrupt the renaming such as a signal from another core holding the cache, the rename just naturally retires beyond a certain point. Read Morris Marden's 2014 patent on it for more details. https://patentimages.storage.googleapis.com/16/3f/47/ea087053376a3a/US20140095814A1.pdf https://patentimages.storage.googleapis.com/16/3f/47/ea08705...
- millstone 6y agoHmm, what's the advantage of doing memory renaming for unretired stores? Won't the value just be forwarded from the store buffer? The patent is a great resource, thanks for that. But I think it supports my point when it suggests that memory renaming may persist indefinitely: Alternatively, reclamation of the original physical register could be delayed to facilitate later memory renaming. and later: ...the MRT may always retain physical registers of N past store operations...the physical register is reclaimed to the free list when it exits the MRT, for example, when it is no longer one of the N most recent store operations. So it's possible. I don't think we know from Agner's work whether AMD went this route or not.
- gpderetta 6y agoStore forwarding is slower, it is usually as fast a reading from L1 directly in the best case (4-5 cycles). This optimization has a latency of 0-1 cycles.
- avianes 6y agoIn order for memory mirroring to be enabled, the memory must probably be read first since its value must be used. The processor must then ask the cache controller to acquire the cache-line in a "no writer / multiple reader" mode ("S" state). If another processor wants to write to this cache-line it must first take the cache-line in "single writer / no reader" mode ("M" state) which invalidates the cache-line in all other caches. In the processor performing the memory mirroring, if the cache-line goes out of the "S" state then the processor cannot read the cache-line anymore and memory mirroring has to stop since it reads this memory. In order to continue it must ask for the cache-line again, read it again, and then get an updated value. It's just a guess, but that's probably what happens in order for the memory mirroring not to break the cache-coherency. So "yes, there is such logic", but it already existed in the processor to avoid the same problem when data is in the cache. And so, there would be no additional logic to handle this.