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Modern CPUs don’t have RISC cores, complex instructions are all the way down. On current-gen CPUs, only rarely used instructions are decoded into multiple micr
by Const-me 6y ago
Modern CPUs don’t have RISC cores, complex instructions are all the way down.
On current-gen CPUs, only rarely used instructions are decoded into multiple micro-ops, the majority of them decode into a single micro-op, even when they do many things at once like memory load + compute. More often the opposite happens, multiple AMD64 instructions are merged into a single micro-op, this is called “micro-ops fusion”.
- gpderetta 6y ago> multiple AMD64 instructions are merged into a single micro-op, this is called “micro-ops fusion”. very minor nit: it is actually called 'macro-op fusion', 'micro-op fusion' is when ops from a single instruction are put back together in part of the pipeline. Otherwise, spot on.
- dragontamer 6y ago> Modern CPUs don’t have RISC cores, complex instructions are all the way down. Proof: Intel's LEA instruction is executed as one uop. That's a super complicated instruction that you'd expect to be split into other uops, but... lo and behold, complex all the way down to the end silicon. Even a "risc" machine: ARM has macro-op fusion, with AESE / AESMC instructions. (Macro-op fuse AESE / AESMC into a singular AES macro-op. A full AES cycle includes both steps, so its very rare to ever need to only do one of the steps). As such, I've considered "RISC" to be a misnomer. Even RISC-V and ARM are now doing macro-op fusion (and micro-ops). So what exactly is RISC mean anyway?
- saagarjha 6y agoYou can't do an operation on something in memory directly?
- dragontamer 6y agoThat's just "Load/Store Architecture" though. RISC machines are usually load/store, but so are a bunch of other things, like GPUs and such. Hardly unique to RISC.