If you are relying on that behaviour then your code is already broken on most modern x86 processors due to their memory ordering implementations. The store to

If you are relying on that behaviour then your code is already broken on most modern x86 processors due to their memory ordering implementations. The store to the address at rsi will actually go in to the processor's store buffer and the subsequent add is allowed to retrieve the value from the store buffer _before_ it's drained to main memory. Under TSO, AMD's memory mirroring implementation here is totally fine. It could potentially change observable behaviour if you could turn it on or off but this is irrelevant given you wil see changes in observable behaviour for that same snippet of code depending on which microarchitecture of AMD or Intel processor you choose to run it on. It's worth having a read on the details for different memory models and how they relate to implements. This seems like a good guide: https://www.cs.utexas.edu/~bornholt/post/memory-models.html https://www.cs.utexas.edu/~bornholt/post/memory-models.html