10 ms·

If you have multiple cores then the OS’s scheduler doesn’t matter much. In one thread, do a loop of: loop: movq [rsi], 10 addq [rsi], 5 cmpq [rsi], 15

If you have multiple cores then the OS’s scheduler doesn’t matter much. In one thread, do a loop of: loop: movq [rsi], 10 addq [rsi], 5 cmpq [rsi], 15 jeq loop (Or however you write that with correct assembler). In another thread with the same value in rsi, do: loop: movq [rsi], 100 jmp loop Ensure these threads run on different cores. You would expect the loop in the first thread to eventually terminate. The probability distribution of the time it takes to terminate would probably be informative. Would it terminate on this and chip? How would the distribution be different?

byefruit 6y ago
If you are relying on that behaviour then your code is already broken on most modern x86 processors due to their memory ordering implementations. The store to the address at rsi will actually go in to the processor's store buffer and the subsequent add is allowed to retrieve the value from the store buffer _before_ it's drained to main memory. Under TSO, AMD's memory mirroring implementation here is totally fine. It could potentially change observable behaviour if you could turn it on or off but this is irrelevant given you wil see changes in observable behaviour for that same snippet of code depending on which microarchitecture of AMD or Intel processor you choose to run it on. It's worth having a read on the details for different memory models and how they relate to implements. This seems like a good guide: https://www.cs.utexas.edu/~bornholt/post/memory-models.html https://www.cs.utexas.edu/~bornholt/post/memory-models.html
- deleted 6y ago
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chrisseaton 6y ago
> You would expect the loop in the first thread to eventually terminate. Why would you expect it to eventually terminate? There is nothing in the architecture that should lead you to expect that. The architecture does not guarantee that instructions from the first loop will be interleaved with the second in any particular way, no matter what cores they're running on. > The probability distribution of the time it takes to terminate would probably be informative. But again... the architecture does not guarantee the set of or probability of distribution of interleavings. You cannot write a sound program using this information.
xxs 6y ago
You need some form of barrier (lock/mfence/cpuid) prior to compare instruction to make the snippet correct.

byefruit 6y ago

If you are relying on that behaviour then your code is already broken on most modern x86 processors due to their memory ordering implementations. The store to the address at rsi will actually go in to the processor's store buffer and the subsequent add is allowed to retrieve the value from the store buffer _before_ it's drained to main memory. Under TSO, AMD's memory mirroring implementation here is totally fine. It could potentially change observable behaviour if you could turn it on or off but this is irrelevant given you wil see changes in observable behaviour for that same snippet of code depending on which microarchitecture of AMD or Intel processor you choose to run it on. It's worth having a read on the details for different memory models and how they relate to implements. This seems like a good guide: https://www.cs.utexas.edu/~bornholt/post/memory-models.html https://www.cs.utexas.edu/~bornholt/post/memory-models.html

deleted 6y ago
[deleted]

chrisseaton 6y ago

> You would expect the loop in the first thread to eventually terminate. Why would you expect it to eventually terminate? There is nothing in the architecture that should lead you to expect that. The architecture does not guarantee that instructions from the first loop will be interleaved with the second in any particular way, no matter what cores they're running on. > The probability distribution of the time it takes to terminate would probably be informative. But again... the architecture does not guarantee the set of or probability of distribution of interleavings. You cannot write a sound program using this information.

xxs 6y ago

You need some form of barrier (lock/mfence/cpuid) prior to compare instruction to make the snippet correct.