4 ms·

On most x86 chips since the Pentium Pro (and the K6 for AMD, IIRC) the machine code instructions which are visible to the programmer are turned into "micro oper

by ch_123 6y ago

On most x86 chips since the Pentium Pro (and the K6 for AMD, IIRC) the machine code instructions which are visible to the programmer are turned into "micro operations" by the CPU's instruction decoder. See here for a introduction: https://en.wikipedia.org/wiki/Micro-operation https://en.wikipedia.org/wiki/Micro-operation

Waterluvian 6y ago
Thanks for the link! So on older chips, like maybe an 8080, I could expect to see literal hardware implementations of instructions?
- klelatti 6y ago
  Ken Shirriff has an excellent series of blog posts on early Intel chips (running from 4004 to 8086 I think). Don't believe he's done one on the 8080 but the post on the 8008 is great [1] and I'd expect that the 8080 (which followed it and was designed by the same team) is very similar. In short no microcode but there is a PLA (Programmable Logic Array) which helps to decode the instructions. [1] http://www.righto.com/2016/12/die-photos-and-analysis-of_24.html http://www.righto.com/2016/12/die-photos-and-analysis-of_24....
  - kens 6y ago
    Thanks for the nice comment! I haven't looked into the 8080 because other people have examined it in detail. See https://news.ycombinator.com/item?id=24101956 https://news.ycombinator.com/item?id=24101956 for an exact Verilog representation of the 8080.
- Const-me 6y ago
  Modern CPUs don’t have RISC cores, complex instructions are all the way down. On current-gen CPUs, only rarely used instructions are decoded into multiple micro-ops, the majority of them decode into a single micro-op, even when they do many things at once like memory load + compute. More often the opposite happens, multiple AMD64 instructions are merged into a single micro-op, this is called “micro-ops fusion”.
  - gpderetta 6y ago
    > multiple AMD64 instructions are merged into a single micro-op, this is called “micro-ops fusion”. very minor nit: it is actually called 'macro-op fusion', 'micro-op fusion' is when ops from a single instruction are put back together in part of the pipeline. Otherwise, spot on.
  - dragontamer 6y ago
    > Modern CPUs don’t have RISC cores, complex instructions are all the way down. Proof: Intel's LEA instruction is executed as one uop. That's a super complicated instruction that you'd expect to be split into other uops, but... lo and behold, complex all the way down to the end silicon. Even a "risc" machine: ARM has macro-op fusion, with AESE / AESMC instructions. (Macro-op fuse AESE / AESMC into a singular AES macro-op. A full AES cycle includes both steps, so its very rare to ever need to only do one of the steps). As such, I've considered "RISC" to be a misnomer. Even RISC-V and ARM are now doing macro-op fusion (and micro-ops). So what exactly is RISC mean anyway?
    - saagarjha 6y ago
      You can't do an operation on something in memory directly?
      - dragontamer 6y ago
        That's just "Load/Store Architecture" though. RISC machines are usually load/store, but so are a bunch of other things, like GPUs and such. Hardly unique to RISC.
PixelOfDeath 6y ago
The K5 was actually a RISC CPU with an x86 decoder on top. So we can count that one, too?!

by ch_123 6y ago

Waterluvian 6y ago

Thanks for the link! So on older chips, like maybe an 8080, I could expect to see literal hardware implementations of instructions?

klelatti 6y ago
Ken Shirriff has an excellent series of blog posts on early Intel chips (running from 4004 to 8086 I think). Don't believe he's done one on the 8080 but the post on the 8008 is great [1] and I'd expect that the 8080 (which followed it and was designed by the same team) is very similar. In short no microcode but there is a PLA (Programmable Logic Array) which helps to decode the instructions. [1] http://www.righto.com/2016/12/die-photos-and-analysis-of_24.html http://www.righto.com/2016/12/die-photos-and-analysis-of_24....
- kens 6y ago
  Thanks for the nice comment! I haven't looked into the 8080 because other people have examined it in detail. See https://news.ycombinator.com/item?id=24101956 https://news.ycombinator.com/item?id=24101956 for an exact Verilog representation of the 8080.
Const-me 6y ago
Modern CPUs don’t have RISC cores, complex instructions are all the way down. On current-gen CPUs, only rarely used instructions are decoded into multiple micro-ops, the majority of them decode into a single micro-op, even when they do many things at once like memory load + compute. More often the opposite happens, multiple AMD64 instructions are merged into a single micro-op, this is called “micro-ops fusion”.
- gpderetta 6y ago
  > multiple AMD64 instructions are merged into a single micro-op, this is called “micro-ops fusion”. very minor nit: it is actually called 'macro-op fusion', 'micro-op fusion' is when ops from a single instruction are put back together in part of the pipeline. Otherwise, spot on.
- dragontamer 6y ago
  > Modern CPUs don’t have RISC cores, complex instructions are all the way down. Proof: Intel's LEA instruction is executed as one uop. That's a super complicated instruction that you'd expect to be split into other uops, but... lo and behold, complex all the way down to the end silicon. Even a "risc" machine: ARM has macro-op fusion, with AESE / AESMC instructions. (Macro-op fuse AESE / AESMC into a singular AES macro-op. A full AES cycle includes both steps, so its very rare to ever need to only do one of the steps). As such, I've considered "RISC" to be a misnomer. Even RISC-V and ARM are now doing macro-op fusion (and micro-ops). So what exactly is RISC mean anyway?
  - saagarjha 6y ago
    You can't do an operation on something in memory directly?
    - dragontamer 6y ago
      That's just "Load/Store Architecture" though. RISC machines are usually load/store, but so are a bunch of other things, like GPUs and such. Hardly unique to RISC.

PixelOfDeath 6y ago

The K5 was actually a RISC CPU with an x86 decoder on top. So we can count that one, too?!