TSMC's 5nm 'N5' process -the highest density process currently shipping- has a raw transistor density of 173 million per millimeter^2. (https://en.wikipedia.org

TSMC's 5nm 'N5' process -the highest density process currently shipping- has a raw transistor density of 173 million per millimeter^2. (https://en.wikipedia.org/wiki/5_nm_process https://en.wikipedia.org/wiki/5_nm_process) If the transistors were laid out on a square grid (they aren't - it's rectangular), each square would be 76nm on a side. This area includes the transistor itself, the contact area (to connect the transistor to wires) and the required spacing to prevent the transistors from interfering with each other.