5 ms·

Once upon a time (the "Dennard Scaling Era") VLSI circuit design used the same relative geometry at different "feature sizes" - all dimensions of the design(wir

Once upon a time (the "Dennard Scaling Era") VLSI circuit design used the same relative geometry at different "feature sizes" - all dimensions of the design(wire width, wire spacing, gate length, gate pitch, ..., etc.) scaled by the same amount from generation to generation, so it was possible to completely specify the transistor layout with a single dimension (generally called 'L'), and derive all other measurements from that as a multiple of 'L'. Transistor density was proportional to 1/L^2. The measurement that was used originally for 'L' was the gate length. As designs shrunk below 40nm, it became impossible to shrink _every_ dimension proportionally. In particular, for planar silicon, gate length stops shrinking around ~30nm, but other things could still shrink. This meant that transistor density could still increase, but the relative geometry of wires/gates/spacing/etc. had to change, so it was no longer possible to specify the full geometry with a single number. But people liked the single number as a handy way of comparing processes, so marketing kept using it as a way to compare processes. The way they decided to do that was mostly to try and keep the proportionality between the transistor density of a process and 1/L^2. To the extent a "feature size" number of a process means anything, it means "the relative transistor density of this process is equivalent to what you would get if you had used the old (>40nm) geometry, and shrunk 'L' to the specified feature size". Even that relationship has degraded in recent years - now it's more like "we calculate the new feature size as the size of the previous process divided by sqrt(2)". Regardless, as stated in the parent, there is no single dimension of any recent process that corresponds to the '3nm' number. There's lots of resources online that describe this, but for an overview, you could start here (describes pre- and post-Dennard scaling): http://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-4-Scaling.pdf http://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-4-Sca...

ur-whale 6y ago
Thanks for that explanation. What would be even more useful is an actual answer to the underlying question the OP seems to be making: how much further until one of the many dimensions you are talking about simply runs out of Si atoms? In other words, however "made-up" the 3nm marketing number may be, physics limits should still dictate a lower bound for it, and the OP seems to be wondering what that is.
- egsmi 6y ago
  It depends on how one defines transistor, but if the definition of voltage controlled switch is sufficient then one atom will do. https://en.wikipedia.org/wiki/Single-atom_transistor https://en.wikipedia.org/wiki/Single-atom_transistor This has nothing to do with the mass produced transistors (yet!) those are 10s of nm across even in 3 or 5nm.
- garmaine 6y ago
  There isn't an answer to that. We've already hit physical scaling limits for the old style (>40nm) of transistor manufacturing. Each successive generation since then has employed new tricks to improve performance, and each jump in performance is labeled with a smaller process node size number. This can keep going so long as there are more optimizations to be found. And since not all process optimizations involve shrinking dimensions, it's not necessarily the case that we can predict from physical principles when this will end. For example, stacked chips are increasingly being used but are fundamentally limited by heat transport. Maybe when we get into sub-1nm "sizes" the process nodes will be defined by how well they transport heat out of volumetric chip designs? Or we'll switch to twisted graphene superconductors for certain components which increases efficiency without necessarily shrinking feature sizes. Etc. I'm just throwing those possibilities out. The point is we can't predict when scaling will ultimately end.
- wtallis 6y ago
  That's still not a straightforward question to answer, because transistor shrinks aren't just about shrinking some dimensions while others stay at their limits. Transistor geometry has changed in more fundamental ways. Beyond ~28nm, the industry switched from planar transistors to FinFETs, so now instead of gate width we have an extra dimension and have to consider stuff like fin height and fin thickness and pitch. Starting around 3nm, we'll be seeing "gate all around" transistors—GAA FETs, in the form of nanowire, nanoribbon or nanosheets.
egsmi 6y ago
Nice explanation. One can see an example of the scalable CMOS design rules on slides 10 and 11 of this deck. https://inst.eecs.berkeley.edu/~cs250/fa09/lectures/lec01.pdf https://inst.eecs.berkeley.edu/~cs250/fa09/lectures/lec01.pd... (To the casual reader: Note how the dimensions all have no unit. There are measured in L as indicated by the parent.)
fossuser 6y ago
> "Regardless, as stated in the parent, there is no single dimension of any recent process that corresponds to the '3nm' number." That's interesting - are they just entirely making that up then? What's the 3nm supposed to represent? It seems like it's one thing to pick a specific dimension length to measure even if it's not proportional to all of the others, and another to just pick one that isn't represented at all.
- egsmi 6y ago
  3nm and 5nm are just marketing names it does not represent any geometry of the transistor. Probably the best analogy is 3nm would be the average length of the side of a pixel. One draws a transistor, or anything else, from many pixels. The exact details are under NDA but to get a 'very' approximate idea of the scale of things one can look at the 5nm Wikipedia page. They list the metal pitch as 30nm in TSMC's N5 node so in general two pieces of metal cannot be within 6 'pixels' of one another. One gets a rough guess on the distance between transistors by looking at the gate pitch (roughly 10 pixels in this case) but that measurement comes with a lot of caveats too. Keep in mind this is when you're going out of your way to make something tiny but there are many good electrical engineering reasons to make the transistors larger still, and quite a lot of them are. https://en.wikipedia.org/wiki/5_nm_process https://en.wikipedia.org/wiki/5_nm_process
  - fomine3 6y ago
    Wikichip is also great. https://en.wikichip.org/wiki/5_nm_lithography_process https://en.wikichip.org/wiki/5_nm_lithography_process
- garmaine 6y ago
  > That's interesting - are they just entirely making that up then? What's the 3nm supposed to represent? A progression over 5nm. That is all.
mrfusion 6y ago
So how big is a modern transistor? How close to together do the transistors get? Does this mean there’s actually a lot more room to shrink things?
- variaga 6y ago
  TSMC's 5nm 'N5' process -the highest density process currently shipping- has a raw transistor density of 173 million per millimeter^2. (https://en.wikipedia.org/wiki/5_nm_process https://en.wikipedia.org/wiki/5_nm_process) If the transistors were laid out on a square grid (they aren't - it's rectangular), each square would be 76nm on a side. This area includes the transistor itself, the contact area (to connect the transistor to wires) and the required spacing to prevent the transistors from interfering with each other.
lisardo 6y ago
That was really instructive. Thank you for sharing.

ur-whale 6y ago

Thanks for that explanation. What would be even more useful is an actual answer to the underlying question the OP seems to be making: how much further until one of the many dimensions you are talking about simply runs out of Si atoms? In other words, however "made-up" the 3nm marketing number may be, physics limits should still dictate a lower bound for it, and the OP seems to be wondering what that is.

egsmi 6y ago
It depends on how one defines transistor, but if the definition of voltage controlled switch is sufficient then one atom will do. https://en.wikipedia.org/wiki/Single-atom_transistor https://en.wikipedia.org/wiki/Single-atom_transistor This has nothing to do with the mass produced transistors (yet!) those are 10s of nm across even in 3 or 5nm.
garmaine 6y ago
There isn't an answer to that. We've already hit physical scaling limits for the old style (>40nm) of transistor manufacturing. Each successive generation since then has employed new tricks to improve performance, and each jump in performance is labeled with a smaller process node size number. This can keep going so long as there are more optimizations to be found. And since not all process optimizations involve shrinking dimensions, it's not necessarily the case that we can predict from physical principles when this will end. For example, stacked chips are increasingly being used but are fundamentally limited by heat transport. Maybe when we get into sub-1nm "sizes" the process nodes will be defined by how well they transport heat out of volumetric chip designs? Or we'll switch to twisted graphene superconductors for certain components which increases efficiency without necessarily shrinking feature sizes. Etc. I'm just throwing those possibilities out. The point is we can't predict when scaling will ultimately end.
wtallis 6y ago
That's still not a straightforward question to answer, because transistor shrinks aren't just about shrinking some dimensions while others stay at their limits. Transistor geometry has changed in more fundamental ways. Beyond ~28nm, the industry switched from planar transistors to FinFETs, so now instead of gate width we have an extra dimension and have to consider stuff like fin height and fin thickness and pitch. Starting around 3nm, we'll be seeing "gate all around" transistors—GAA FETs, in the form of nanowire, nanoribbon or nanosheets.

egsmi 6y ago

Nice explanation. One can see an example of the scalable CMOS design rules on slides 10 and 11 of this deck. https://inst.eecs.berkeley.edu/~cs250/fa09/lectures/lec01.pdf https://inst.eecs.berkeley.edu/~cs250/fa09/lectures/lec01.pd... (To the casual reader: Note how the dimensions all have no unit. There are measured in L as indicated by the parent.)

fossuser 6y ago

> "Regardless, as stated in the parent, there is no single dimension of any recent process that corresponds to the '3nm' number." That's interesting - are they just entirely making that up then? What's the 3nm supposed to represent? It seems like it's one thing to pick a specific dimension length to measure even if it's not proportional to all of the others, and another to just pick one that isn't represented at all.

egsmi 6y ago
3nm and 5nm are just marketing names it does not represent any geometry of the transistor. Probably the best analogy is 3nm would be the average length of the side of a pixel. One draws a transistor, or anything else, from many pixels. The exact details are under NDA but to get a 'very' approximate idea of the scale of things one can look at the 5nm Wikipedia page. They list the metal pitch as 30nm in TSMC's N5 node so in general two pieces of metal cannot be within 6 'pixels' of one another. One gets a rough guess on the distance between transistors by looking at the gate pitch (roughly 10 pixels in this case) but that measurement comes with a lot of caveats too. Keep in mind this is when you're going out of your way to make something tiny but there are many good electrical engineering reasons to make the transistors larger still, and quite a lot of them are. https://en.wikipedia.org/wiki/5_nm_process https://en.wikipedia.org/wiki/5_nm_process
- fomine3 6y ago
  Wikichip is also great. https://en.wikichip.org/wiki/5_nm_lithography_process https://en.wikichip.org/wiki/5_nm_lithography_process
garmaine 6y ago
> That's interesting - are they just entirely making that up then? What's the 3nm supposed to represent? A progression over 5nm. That is all.

mrfusion 6y ago

So how big is a modern transistor? How close to together do the transistors get? Does this mean there’s actually a lot more room to shrink things?

variaga 6y ago
TSMC's 5nm 'N5' process -the highest density process currently shipping- has a raw transistor density of 173 million per millimeter^2. (https://en.wikipedia.org/wiki/5_nm_process https://en.wikipedia.org/wiki/5_nm_process) If the transistors were laid out on a square grid (they aren't - it's rectangular), each square would be 76nm on a side. This area includes the transistor itself, the contact area (to connect the transistor to wires) and the required spacing to prevent the transistors from interfering with each other.

lisardo 6y ago

That was really instructive. Thank you for sharing.