The clock signal is not sent because it would require another high-bandwidth wire and would introduce problems of clock skew within a lane. In other words, havi

The clock signal is not sent because it would require another high-bandwidth wire and would introduce problems of clock skew within a lane. In other words, having a separate clock means you need to ensure that the clock and data signals are synchronized at the receiver, which is pretty difficult to achieve. PCIe has this problem for lane-to-lane skew, but not within a lane. The limit for lane-to-lane skew is 1.6 ns. If each lane might also have similar skew between the data and clock, then the per-lane bandwidth would be limited to a few hundred megabits per second (instead of the achieved gigabits per second).