3 ms·
I'm not the person you asked, but I made an educational simulator for RISC-V [0]. The most critical resource even if it is not super convenient is the official
by thethirdone 6y ago
I'm not the person you asked, but I made an educational simulator for RISC-V [0].
The most critical resource even if it is not super convenient is the official RISC-V specification [1] (this is the latest draft as of writing this comment).
There are a bunch of open source simulators [2] to look at for reference if you are unsure of how something is suppose to work. I would recommend compiling a C program to RISC-V and looking at disassembled machine code to get an idea for how things are normally done in terms of RISC-V assembly.
There isn't any particularly nice documentation that I am aware of, but enough universities teach using it that there should be some resources that would be helpful for making a simulator. I can probably come up with some links if you are serious about making a simulator, but its a little too much effort to do for a drive-by comment.
[0]: https://github.com/TheThirdOne/rars https://github.com/TheThirdOne/rars
[1]: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20200727-8088ba4/riscv-spec.pdf https://github.com/riscv/riscv-isa-manual/releases/download/...
[2]: https://github.com/riscv/riscv-software-list#simulators https://github.com/riscv/riscv-software-list#simulators
- charlesdaniels 6y agoHey, thanks for making RARS! I am TA-ing a class this semester where we are using RARS. It's my university's "build a CPU with Verilog class", and we just switched to RISC-V. We previously used MIPS with MARS, and lacking a MARS alternative was one of our blockers for switching to RISC-V.