That depends on the CPU. In RISC-V's case, you cannot jump to an arbitrary address conditionally at all, you have to use a branch instruction. B-type instructi

That depends on the CPU. In RISC-V's case, you cannot jump to an arbitrary address conditionally at all, you have to use a branch instruction. B-type instructions have only a 12-bit immediate value (technically 13 bits with an implied 0 in the lowest order bit), which means it can only code for jumps up to +- 1024 words away (IIRC, this 13 bit value codes for a jump up to +- 2048 half-words away, but RISC-V instructions are full words, hence 1024... using the 16-bit extensions would change things I think). RISC-V J-types have a 20 bit jump target addressing relative half-words giving you a range of 2^20 / (2 * 2) = +- 262144 full words. Alternative you could use JALR, which will let you jump to any 32-bit address, but then you would have potentially up to 4 instructions for a conditional jump (blt, luo, ori, jalr). To my recollection, MIPS is similar but has a larger immediate field for J-types. I'm not familiar enough with other arches to be comment on them. The way you would code for a conditional jump to a far away target would be to use a conditional branch, which either skips over or runs an unconditional jump. If using JALR as described, you might have something like: ... blt t1, t2, jump_not_taken lui t3, 0x1234 # upper 20 bits of jump target ori t3, 0x456 # lower 12 bits of jump target jalr t3 jump_not_taken: ... To answer the question more concisely, something like JL would probably end up being an assembler pseudo-instruction. For example in RISC-V there is no BGE instruction, it compiles to a BLE with the operands swapped. This reduces overhead in the instruction encoding, and is equivalent. AMD64/IA32 are probably different, but I don't know. And of course you could always define a CPU architecture with something like "conditional jump to register value" (JALRLT for example). I don't know if anybody has though. Source: https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/ Edit: in the time it too me to write this, somebody did the same thing for x86: https://news.ycombinator.com/item?id=24256275 https://news.ycombinator.com/item?id=24256275