I like this. Real FPGAs use the same realization of an n-input LUT as a 2^n bit shift register plus a mux, which is why e.g. Xilinx lets you have an SRL16 for t

I like this. Real FPGAs use the same realization of an n-input LUT as a 2^n bit shift register plus a mux, which is why e.g. Xilinx lets you have an SRL16 for the same cost as a LUT4--the shift register is primarily intended to hold the LUT configuration bitstream, but you can repurpose it as user logic.