3 ms·
Still wondering how they’ve handled interconnecting beyond each reticle limit/exposure. Are they staggering the exposures for each layer? And how do they handle
by evancox100 6y ago
Still wondering how they’ve handled interconnecting beyond each reticle limit/exposure. Are they staggering the exposures for each layer? And how do they handle packaging/IO/power delivery?
I guess these are the secret sauces and we are unlikely to get in depth information.
- gary_0 6y agoIn the PDF[0] that aveni linked above, they mention they "add wires across scribe line in partnership with TSMC, Extend 2D mesh across die". So the wafer isn't exactly one big chip. [0] https://www.hotchips.org/hc31/HC31_1.13_Cerebras.SeanLie.v02.pdf https://www.hotchips.org/hc31/HC31_1.13_Cerebras.SeanLie.v02...
- wmf 6y agoI think reticle stitching has been done previously in image sensors and silicon interposers so it may be an evolution of that.