Have they improved Load-Hit-Store penalties from previous generations? Lots of transistors and opcodes have been sacrificed for fancy things like transactional

Have they improved Load-Hit-Store penalties from previous generations? Lots of transistors and opcodes have been sacrificed for fancy things like transactional memory, runtime instrumentation and other features but fundamentals haven't improved requiring expensive compiler opts which interpreters don't do and are expensive for JITs. The Intel chips did the fundamentals better, has POWER caught up?