Well yes and no - at the time the 8086 was designed gate capacitance dominated over wire RC delays - early design tools (sort of pre-late 90s, way after the ori

Well yes and no - at the time the 8086 was designed gate capacitance dominated over wire RC delays - early design tools (sort of pre-late 90s, way after the original 8086) didn't bother with calculating RC delays during synthesis and we only really dealt with them in late static timing analysis (and really then only for a few long lines). Essentially as chip features got smaller wire resistance didn't scale the same as gate capacitance (partly it's edge effects) and our tools needed to change as RC delays started to dominate