3 ms·

I've loved following this series of posts as an amateur/layman wanting to know more about the hardware behind the chips I use! Here's a question for anyone who

I've loved following this series of posts as an amateur/layman wanting to know more about the hardware behind the chips I use! Here's a question for anyone who might have an interest to help me understand (at a high summary level) -- Steady DC power is being provided to the chip, and the internal clock is going at 5 Mhz. What are the input and output signals like? Are they on the order of a few kHz and in a long stream of data (in a short burst?) that the CPU then takes and works on until the "delivery" burst? Is this the FSB? How many of the 45 wires coming off the CPU are for the input/output signals, or what are the rest of them for? Thanks!

kens 6y ago
The 8086 has 40 external pins [1]. There are 20 address lines shared with 16 data lines, so it's a 16-bit computer that can address 1 megabyte. The remaining pins are mostly assorted control signals. (Intel liked to keep the pin count pointlessly low, so the pins are multiplexed and have several uses.) The external pins are switching at the 5 MHz clock speed, and there are four clock periods for one memory bus cycle. The address pins send out the address the first cycle, wait a cycle for memory to respond, and read or write the data the third cycle. The CPU and the memory bus are working at the same clock speed. (Although somewhat decoupled because the 8086 had prefetching.) I think you're going the wrong direction with kHz I/O and delivery bursts. I've simplified things a bit. The 8086 User's Manual [2] explains all the signals in great detail if you really want to know. [1] I see that you carefully counted the 45 wires off the die. The power and two grounds each use two bond wires in parallel for more current. There are two wires to bias the substrate. So that's the "extra" 5 wires. [2] http://www.bitsavers.org/components/intel/_dataBooks/1981_iAPX_86_88_Users_Manual.pdf http://www.bitsavers.org/components/intel/_dataBooks/1981_iA...
- supernova87a 6y ago
  Thanks! I will have a read through that manual!

kens 6y ago

The 8086 has 40 external pins [1]. There are 20 address lines shared with 16 data lines, so it's a 16-bit computer that can address 1 megabyte. The remaining pins are mostly assorted control signals. (Intel liked to keep the pin count pointlessly low, so the pins are multiplexed and have several uses.) The external pins are switching at the 5 MHz clock speed, and there are four clock periods for one memory bus cycle. The address pins send out the address the first cycle, wait a cycle for memory to respond, and read or write the data the third cycle. The CPU and the memory bus are working at the same clock speed. (Although somewhat decoupled because the 8086 had prefetching.) I think you're going the wrong direction with kHz I/O and delivery bursts. I've simplified things a bit. The 8086 User's Manual [2] explains all the signals in great detail if you really want to know. [1] I see that you carefully counted the 45 wires off the die. The power and two grounds each use two bond wires in parallel for more current. There are two wires to bias the substrate. So that's the "extra" 5 wires. [2] http://www.bitsavers.org/components/intel/_dataBooks/1981_iAPX_86_88_Users_Manual.pdf http://www.bitsavers.org/components/intel/_dataBooks/1981_iA...

supernova87a 6y ago
Thanks! I will have a read through that manual!