3 ms·
That's interesting. The datasheet says the clock has to be 2/3 low and 1/3 high with just 17 ns of margin. It's surprising that the datasheet is so strict if yo
by kens 6y ago
That's interesting. The datasheet says the clock has to be 2/3 low and 1/3 high with just 17 ns of margin. It's surprising that the datasheet is so strict if you can totally violate the specification and still have it work.
(To be clear, I'm not disagreeing with you that this works.)
- jhallenworld 6y agoWell the spec is minimum cycle time = 200 ns, maximum cycle time 500 ns. But also it has min. low time = 118 ns and min. high time = 69 ns, which is how the 1/3 duty cycle shows up. But there is no spec violation with, for example, low time = 125 ns, high time = 125 ns for a cycle time of 250 ns (4 MHz).
- kens 6y agoWhich spec are you looking at? Is it a later revision? I'm looking at the User's Manual [1] which says the CLK Low Time has a minimum of (2/3 cycle time)-15 and CLK High Time has a minimum of (1/3 cycle time)+2. That yields a minimum low time of 151 ns which is violated by the 125 ns value. [1] page B-18 in http://www.bitsavers.org/components/intel/_dataBooks/1981_iAPX_86_88_Users_Manual.pdf http://www.bitsavers.org/components/intel/_dataBooks/1981_iA...
- jhallenworld 6y agoThis one, page 15: https://course.ece.cmu.edu/~ece740/f11/lib/exe/fetch.php?media=wiki:8086-datasheet.pdf https://course.ece.cmu.edu/~ece740/f11/lib/exe/fetch.php?med... Ah, I see in the older datasheet it says TCLCH = 2/3 * TCLCL - 15. But I'm pretty sure they mean TCLCH = 2/3 * TCLCLmin - 15 which gives the 118 ns it has in the newer datasheet.
- kens 6y agoThanks! That makes more sense.