I recently read the book Principles of Power Integrity for PDN Design and it talks about the same problem from a perspective of a board designer. The authors me

I recently read the book Principles of Power Integrity for PDN Design and it talks about the same problem from a perspective of a board designer. The authors mention that in the vast majority of chips, due to the bond wire inductance alone, board-level bypass is useless at frequencies above 100 MHz. The only solution here is adding on-die capacitance, otherwise it's not possible for a modern chip to operate correctly. In practice, the on-die capacitance is often minimum due to its high cost, only effective at frequencies above 100 MHz, leaving an anti-resonate peak around 100 MHz, thus the problem can never be eliminated (unless a better package or more on-die capacitance is used, which is not implemented due to its costs). And the author showed how you can break almost every power distribution network of a FPGA, by switching logic circuits in code at the exact anti-resonate frequency where bypassing is least effective. Although it's usually not a problem in practice (until you get "lucky"...). And contrary to popular beliefs, it's impossible to remove it, no matter how many bypass capacitors or how much buried capacitance exists on the circuit board. In a complex chip like FPGA, PDN is critical. The author suggested that the best thing the board designer can do is a workaround: using bypass capacitors of multiple values to "tune" the PDN - this was done as a rule-of-thumb in the old days, and today it's often seen as a bad practice as it creates multiple uncontrolled resonate and anti-resonate frequency spikes when capacitors are combined with parasitic inductance (similar to the case of the 100 MHz peak, but at board level), so at some range of frequencies, impedance is actually significantly increased, which is in conflict of the goal of decreasing PDN impedance at all frequencies. But in the case proposed by the authors, it's done in a controlled manner - the PDN impedance is intentionally increased by carefully creating a flat, slightly higher impedance region around 100 MHz to dampen unwanted oscillation (with simulations and measurements) when it's inadvertently excited. Also, sometimes changing the timings or operating frequencies is required, so the impedance peak of the chip PDN is not excited, even when it means the end-user must redesign firmware, microcode, or HDL code.