4 ms·

This is the one I personally have been waiting for. Thanks! On the power distribution did you notice any bypassing? There are a number of ways to do it now.

by egsmi 6y ago

This is the one I personally have been waiting for. Thanks! On the power distribution did you notice any bypassing? There are a number of ways to do it now. I have no idea how they did it, if at all, in the 70s. Also, did you notice any trim or anything on the clock driver so they could match phase of clock and not clock?

dboreham 6y ago
I never saw bypass caps on chip, in the 80s when I was looking at chips.
kens 6y ago
There's no power bypassing on the chip, just the power lines. There's no clock trimming either. The clock circuitry ensures that there is a gap between the two phases, but there's no adjustment. But at 10 MHz, the clock is not too sensitive.
- egsmi 6y ago
  That’s really interesting. It seems like a foreign world compared to what I’m used to. :)
  - kens 6y ago
    Do you want to say a bit about bypassing and trimming on modern chips?
    - egsmi 6y ago
      It's a lot of information for a forum comment. I will provide a pointer though. I think the book at cmosvlsi.com is pretty good for an introduction to the realities of modern digital IC design. For more information on the topic of this thread in particular see slides 17-19 in this deck. I was asking if the cap on the far right of slide 17 existed in this design. http://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect21.pdf http://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect21.pdf On the trim: When I looked at the two phase timing figure provided I noticed if the bottom path through the clock driver was slower than the top path, due to manufacturing tolerance, then that could cause skew (see slide 24 in the deck I pointed to) between the phases which might cause phase 1 and phase 2 to get too close, or even overlap. The clock driver circuit looked pretty regular in the layout so I was guessing they might have redundant parallel drivers that could be enabled or disabled by the ROM bits which could change the relative strengths of the two paths, after manufacture. This would allow them to recover the part and improve yield. But I guess edge rates and periods were slow enough then that this was not a concern and just relative sizing was enough.
      - segfaultbuserr 6y ago
        I recently read the book Principles of Power Integrity for PDN Design and it talks about the same problem from a perspective of a board designer. The authors mention that in the vast majority of chips, due to the bond wire inductance alone, board-level bypass is useless at frequencies above 100 MHz. The only solution here is adding on-die capacitance, otherwise it's not possible for a modern chip to operate correctly. In practice, the on-die capacitance is often minimum due to its high cost, only effective at frequencies above 100 MHz, leaving an anti-resonate peak around 100 MHz, thus the problem can never be eliminated (unless a better package or more on-die capacitance is used, which is not implemented due to its costs). And the author showed how you can break almost every power distribution network of a FPGA, by switching logic circuits in code at the exact anti-resonate frequency where bypassing is least effective. Although it's usually not a problem in practice (until you get "lucky"...). And contrary to popular beliefs, it's impossible to remove it, no matter how many bypass capacitors or how much buried capacitance exists on the circuit board. In a complex chip like FPGA, PDN is critical. The author suggested that the best thing the board designer can do is a workaround: using bypass capacitors of multiple values to "tune" the PDN - this was done as a rule-of-thumb in the old days, and today it's often seen as a bad practice as it creates multiple uncontrolled resonate and anti-resonate frequency spikes when capacitors are combined with parasitic inductance (similar to the case of the 100 MHz peak, but at board level), so at some range of frequencies, impedance is actually significantly increased, which is in conflict of the goal of decreasing PDN impedance at all frequencies. But in the case proposed by the authors, it's done in a controlled manner - the PDN impedance is intentionally increased by carefully creating a flat, slightly higher impedance region around 100 MHz to dampen unwanted oscillation (with simulations and measurements) when it's inadvertently excited. Also, sometimes changing the timings or operating frequencies is required, so the impedance peak of the chip PDN is not excited, even when it means the end-user must redesign firmware, microcode, or HDL code.

by egsmi 6y ago

dboreham 6y ago

I never saw bypass caps on chip, in the 80s when I was looking at chips.

kens 6y ago

There's no power bypassing on the chip, just the power lines. There's no clock trimming either. The clock circuitry ensures that there is a gap between the two phases, but there's no adjustment. But at 10 MHz, the clock is not too sensitive.

egsmi 6y ago
That’s really interesting. It seems like a foreign world compared to what I’m used to. :)
- kens 6y ago
  Do you want to say a bit about bypassing and trimming on modern chips?
  - egsmi 6y ago
    It's a lot of information for a forum comment. I will provide a pointer though. I think the book at cmosvlsi.com is pretty good for an introduction to the realities of modern digital IC design. For more information on the topic of this thread in particular see slides 17-19 in this deck. I was asking if the cap on the far right of slide 17 existed in this design. http://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect21.pdf http://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect21.pdf On the trim: When I looked at the two phase timing figure provided I noticed if the bottom path through the clock driver was slower than the top path, due to manufacturing tolerance, then that could cause skew (see slide 24 in the deck I pointed to) between the phases which might cause phase 1 and phase 2 to get too close, or even overlap. The clock driver circuit looked pretty regular in the layout so I was guessing they might have redundant parallel drivers that could be enabled or disabled by the ROM bits which could change the relative strengths of the two paths, after manufacture. This would allow them to recover the part and improve yield. But I guess edge rates and periods were slow enough then that this was not a concern and just relative sizing was enough.
    - segfaultbuserr 6y ago
      I recently read the book Principles of Power Integrity for PDN Design and it talks about the same problem from a perspective of a board designer. The authors mention that in the vast majority of chips, due to the bond wire inductance alone, board-level bypass is useless at frequencies above 100 MHz. The only solution here is adding on-die capacitance, otherwise it's not possible for a modern chip to operate correctly. In practice, the on-die capacitance is often minimum due to its high cost, only effective at frequencies above 100 MHz, leaving an anti-resonate peak around 100 MHz, thus the problem can never be eliminated (unless a better package or more on-die capacitance is used, which is not implemented due to its costs). And the author showed how you can break almost every power distribution network of a FPGA, by switching logic circuits in code at the exact anti-resonate frequency where bypassing is least effective. Although it's usually not a problem in practice (until you get "lucky"...). And contrary to popular beliefs, it's impossible to remove it, no matter how many bypass capacitors or how much buried capacitance exists on the circuit board. In a complex chip like FPGA, PDN is critical. The author suggested that the best thing the board designer can do is a workaround: using bypass capacitors of multiple values to "tune" the PDN - this was done as a rule-of-thumb in the old days, and today it's often seen as a bad practice as it creates multiple uncontrolled resonate and anti-resonate frequency spikes when capacitors are combined with parasitic inductance (similar to the case of the 100 MHz peak, but at board level), so at some range of frequencies, impedance is actually significantly increased, which is in conflict of the goal of decreasing PDN impedance at all frequencies. But in the case proposed by the authors, it's done in a controlled manner - the PDN impedance is intentionally increased by carefully creating a flat, slightly higher impedance region around 100 MHz to dampen unwanted oscillation (with simulations and measurements) when it's inadvertently excited. Also, sometimes changing the timings or operating frequencies is required, so the impedance peak of the chip PDN is not excited, even when it means the end-user must redesign firmware, microcode, or HDL code.