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Could you point us to the source of your information please? The Xavier does not support dual-core lockstep afaik. There are other methods in place to detect ra
by jeffreygoesto 6y ago
Could you point us to the source of your information please? The Xavier does not support dual-core lockstep afaik. There are other methods in place to detect random faults, but not that one.
The first widely available ARM cores providing it are fairly new (at least in the automotive domain).
[0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a76ae https://developer.arm.com/ip-products/processors/cortex-a/co...
- my123 6y agoHello, As a person who worked with Xavier for quite a while, dual-core lockstep is supported. Nvidia uses their own CPU cores, not Arm's. See: https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-3231/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/mb1_platform_config_xavier.html https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-323... for how to enable it. > enable_ccplex_lock_step: Boolean; enables or disables CCPLEX dual-core lock step.
- jeffreygoesto 6y agoVery interesting, thank you very much! I know the lockstepped R5s and the dual execution feature of the Carmels (close but no cigar for ISO26262), but not that one. Gonna ask our FAE about it eventually. ;-D
- my123 6y agoNot to get your hopes down... but dual-execution in the Carmels and DCLS for CCPLEX should be references to the same thing. :)
- jeffreygoesto 6y agoAaaah! Ok, so I did not overlook a big feature but knew it under a different name. Thanks for the clarification!