If you get the compiler backend generated then that same description language could also provide optimization hints. If you look at the RISC-V spec a lot is lef

If you get the compiler backend generated then that same description language could also provide optimization hints. If you look at the RISC-V spec a lot is left up to the implementation but certain optimizations leave e.g. instructions available for cache management and this would have to be exposed in the ISA description. Save Intel's compiler, do any rely on implementation details? They rely on cache and fetch details, but only in broad, nebulous ways that seem very portable. There may be open research questions but it seems to me the biggest thing is paying someone to do it.