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Cxxrtl, a Yosys Simulation Back End

• homarp 6y ago
  Yosys, Yosys Open SYnthesis Suite, is a Free Verilog Synthesis Suite.
• krupan 6y ago
  "Once the Yosys gHDL integration stabilize, CXXRTL will be the only open source simulator with mixed Verilog/VHDL language support!" Folks, this is huge! There isn't a single commercial ASIC/SoC project that doesn't have a mix of Verilog and VHDL.