3 ms·

“This bias voltage was dependent on manufacturing variables so was not always the same chip to chip (the goal would be -5VDC). Each chip was tested the and vol

by gen3 6y ago

“This bias voltage was dependent on manufacturing variables so was not always the same chip to chip (the goal would be -5VDC). Each chip was tested the and voltage was hand written on the chip.” Wow! With today’s processor tolerances, that’s crazy to imagine happening. I was also surprised the ALU was an add on. I guess it makes sense if all you need is to control something on a basic level, and not run software. I’m curious how they handled ALU specific instructions if an ALU isn’t present. Does the decode stage just convert them to no-ops?

bryanlarsen 6y ago
Just guessing, but it's probably a memory mapped 74181. The 74181 had 12 input pins: 4 bits to select the operation, and 4 bits each for the two inputs. There were 6 pins of output, 4 bits of data, a carry bit and a comparator bit. Perhaps you'd write to memory mapped latches in front of the inputs and then read the output at a different memory mapped location.
Someone 6y ago
The link is dead for me now, but I browsed it earlier, and got the impression it didn’t have instructions for the ALU, but would write data to the input pins of the ALU and read the result back from the output pins somewhat later. If I interpret appendix C of https://www.hp9845.net/9845/downloads/manuals/Nanoprocessor.pdf https://www.hp9845.net/9845/downloads/manuals/Nanoprocessor.... correctly, that hunch is right.
pwg 6y ago
> I’m curious how they handled ALU specific instructions if an ALU isn’t present. Does the decode stage just convert them to no-ops? There were no ALU specific instructions. The article brushes across how ALU operations were performed, but leaves the explanation for how to the reader to understand. The ALU would have been an I/O device (likely memory mapped I/O [1]) and ALU operations would have been performed by writing data out to the external ALU, waiting for the ALU gate delay, then reading the results back in from the external ALU (i.e., input/output operations): > If you needed support for an ALU you could add one externally (likely with a pair of ‘181 series TTL). Even with an external ALU the Nanoprocessor was very fast. [1] https://en.wikipedia.org/wiki/Memory-mapped_I/O https://en.wikipedia.org/wiki/Memory-mapped_I/O
- monocasa 6y ago
  Yeah, you can see this spelled out more in the block diagrams. Kinda looks like the operands are aliased on the program memory ROM, but I'm not 100% on that.
rathel 6y ago
It seems kind of an inelegant solution to me. They could just solder a resistor to the package at the factory or do some variation of that idea. Now, modern processors are binned, too, depending on the CMOS process corner they turned at. Slow ones have advantages too - leakage is much smaller, so better suited for mobile. Or, in case of some SoC, if it's FF (fast NMOS, fast PMOS), they can reduce core supply by tens of mV. There's even a company specialized in PVT (process, voltage, temperature) monitoring for newest SoC's - Moortec.

by gen3 6y ago

bryanlarsen 6y ago

Just guessing, but it's probably a memory mapped 74181. The 74181 had 12 input pins: 4 bits to select the operation, and 4 bits each for the two inputs. There were 6 pins of output, 4 bits of data, a carry bit and a comparator bit. Perhaps you'd write to memory mapped latches in front of the inputs and then read the output at a different memory mapped location.

Someone 6y ago

The link is dead for me now, but I browsed it earlier, and got the impression it didn’t have instructions for the ALU, but would write data to the input pins of the ALU and read the result back from the output pins somewhat later. If I interpret appendix C of https://www.hp9845.net/9845/downloads/manuals/Nanoprocessor.pdf https://www.hp9845.net/9845/downloads/manuals/Nanoprocessor.... correctly, that hunch is right.

pwg 6y ago

> I’m curious how they handled ALU specific instructions if an ALU isn’t present. Does the decode stage just convert them to no-ops? There were no ALU specific instructions. The article brushes across how ALU operations were performed, but leaves the explanation for how to the reader to understand. The ALU would have been an I/O device (likely memory mapped I/O [1]) and ALU operations would have been performed by writing data out to the external ALU, waiting for the ALU gate delay, then reading the results back in from the external ALU (i.e., input/output operations): > If you needed support for an ALU you could add one externally (likely with a pair of ‘181 series TTL). Even with an external ALU the Nanoprocessor was very fast. [1] https://en.wikipedia.org/wiki/Memory-mapped_I/O https://en.wikipedia.org/wiki/Memory-mapped_I/O

monocasa 6y ago
Yeah, you can see this spelled out more in the block diagrams. Kinda looks like the operands are aliased on the program memory ROM, but I'm not 100% on that.

rathel 6y ago

It seems kind of an inelegant solution to me. They could just solder a resistor to the package at the factory or do some variation of that idea. Now, modern processors are binned, too, depending on the CMOS process corner they turned at. Slow ones have advantages too - leakage is much smaller, so better suited for mobile. Or, in case of some SoC, if it's FF (fast NMOS, fast PMOS), they can reduce core supply by tens of mV. There's even a company specialized in PVT (process, voltage, temperature) monitoring for newest SoC's - Moortec.