I don’t think this is going to answer your question, but I gave a presentation at QCon London this year (back when in person conferences were a thing) on how CP

I don’t think this is going to answer your question, but I gave a presentation at QCon London this year (back when in person conferences were a thing) on how CPU intervals work. In terms of decoding instructions, there’s a stage in the pipeline which estimates the length of the (variable length) instructions and then passes is through to the next stage, which will then try and parse it. A failure here may cause a pipeline stall. Then there are other caches (like the loop stream decoder) which will bypass the instruction parsing for short loops, provided that the start of the loop is aligned to 16-bit. Processors can issue up to 4 wide (5 on recent intel CPUs) but some instructions may only be parsed by the first decoder. ISTR there’s more detail in Agner’s optimisation guides on this. https://www.infoq.com/presentations/microarchitecture-modern-cpu/ https://www.infoq.com/presentations/microarchitecture-modern...