I'm looking into the instruction decoder, but the 8086 is probably too early to answer the questions you're interested in. The 8086 patent [1] is a non-awful pa

I'm looking into the instruction decoder, but the 8086 is probably too early to answer the questions you're interested in. The 8086 patent [1] is a non-awful patent that provides a lot of information, including the instruction decoder. For something slightly more recent, the book "Modern Processor Design" has 40 pages on the microarchitecture of the P6 processor. In brief, the P6 has three decoders running in parallel. An Instruction Length Decoder determines instruction boundaries before decoding, so the decoders receive aligned instructions. Only Decoder 0 can handle complex instructions that require microcode. It can issue 4 micro-ops per cycle, while limited-functionality Decoders 1 and 2 only issue 1 micro-op. The micro-ops are queued with up to 3 micro-ops issued per cycle for execution. [1] https://patents.google.com/patent/US4449184 https://patents.google.com/patent/US4449184