AIUI the group size is a trade-off between the number of independently addressable vectors and the vector size. If the group size were always set to eight then

AIUI the group size is a trade-off between the number of independently addressable vectors and the vector size. If the group size were always set to eight then you could only have four distinct vectors, whereas a group size of one would give you 32 vectors. You want to use the largest group size you can to take full advantage of the hardware, but you're limited by the number of vectors required by your algorithm. This is orthogonal to the size of an element within each vector. The current RISC-V "V" draft standard requires the vector registers to be at least 32 bits wide (VLEN ≥ SLEN ≥ 32)[1], so a 128-bit vector with 16 8-bit elements may require up to four registers. Setting the group size to eight is a bit extravagant, but since the total number of elements was limited to 16 any extra registers in the group will not be affected. With a smaller group size you could potentially use those registers for something else. P.S. I think you have the mask bits reversed. The instruction is "set if greater than" so v1 should be 0x0101010101010000 and v0 should be 0x0000000000000000 (corresponding to the |1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0| state shown in the article for the combined v1:v0 register group). [1] https://github.com/riscv/riscv-v-spec/releases/tag/0.9 https://github.com/riscv/riscv-v-spec/releases/tag/0.9