> it's an implementation detail of Intel CPUs While that may be technically true, since Intel is the only CPU vendor implementing AVX-512, the reason that seve

> it's an implementation detail of Intel CPUs While that may be technically true, since Intel is the only CPU vendor implementing AVX-512, the reason that severe downclocking is warranted is rooted in physics, and may not be resolvable given this ISA design. General vector ISAs like RISC-V "V" may have less trouble, since it is clearer how to design a vector unit not to interfere with scalar access to memory/caches. also, in the article they specifically mention adding shims for several AVX-512 ISAs: > We also have rapidly progressing implementations of many other extensions including NEON, AVX2, SVML, and several AVX-512 extensions (AVX-512F, AVX-512BW, AVX-512VL, etc.). if it's not obvious to you, this means that on machines with AVX-512 hardware will be invoking those instructions directly.