8 ms·

While that's true, I don't see how this is relevant to SIMDe? SIMDe lets you compile code using (e.g.) SSE/AVX intrinsics for ARM targets, using the target plat

While that's true, I don't see how this is relevant to SIMDe? SIMDe lets you compile code using (e.g.) SSE/AVX intrinsics for ARM targets, using the target platform's SIMD intrinsics when possible. It doesn't even officially include support for AVX512 yet. Anyway, for anyone looking for details on what the OP mentioned, it's an implementation detail of Intel CPUs, see https://en.wikichip.org/wiki/intel/frequency_behavior#Base.2C_Non-AVX_Turbo.2C_and_AVX_Turbo https://en.wikichip.org/wiki/intel/frequency_behavior#Base.2...

microcolonel 6y ago
> it's an implementation detail of Intel CPUs While that may be technically true, since Intel is the only CPU vendor implementing AVX-512, the reason that severe downclocking is warranted is rooted in physics, and may not be resolvable given this ISA design. General vector ISAs like RISC-V "V" may have less trouble, since it is clearer how to design a vector unit not to interfere with scalar access to memory/caches. also, in the article they specifically mention adding shims for several AVX-512 ISAs: > We also have rapidly progressing implementations of many other extensions including NEON, AVX2, SVML, and several AVX-512 extensions (AVX-512F, AVX-512BW, AVX-512VL, etc.). if it's not obvious to you, this means that on machines with AVX-512 hardware will be invoking those instructions directly.
gameswithgo 6y ago
This is just an easy to understand fact about SIMD so people always post it.
proverbialbunny 6y ago
While it's not the most relevant, I don't know a lot about SIMD so I'm grateful to hear it.
nemequ1729 6y ago
It does include support for AVX-512, it's just still a work in progress. AVX-512 is enormous (IIRC ~ 4k functions), so it will be a while before it is fully supported. If you're targeting AVX-512 but don't have hardware that supports AVX-512 (like all AMD CPUs), SIMDe can be quite nice. The result is much faster than Intel's SDE and it's just native code that you can use your normal debugger on.

microcolonel 6y ago

> it's an implementation detail of Intel CPUs While that may be technically true, since Intel is the only CPU vendor implementing AVX-512, the reason that severe downclocking is warranted is rooted in physics, and may not be resolvable given this ISA design. General vector ISAs like RISC-V "V" may have less trouble, since it is clearer how to design a vector unit not to interfere with scalar access to memory/caches. also, in the article they specifically mention adding shims for several AVX-512 ISAs: > We also have rapidly progressing implementations of many other extensions including NEON, AVX2, SVML, and several AVX-512 extensions (AVX-512F, AVX-512BW, AVX-512VL, etc.). if it's not obvious to you, this means that on machines with AVX-512 hardware will be invoking those instructions directly.

gameswithgo 6y ago

This is just an easy to understand fact about SIMD so people always post it.

proverbialbunny 6y ago

While it's not the most relevant, I don't know a lot about SIMD so I'm grateful to hear it.

nemequ1729 6y ago

It does include support for AVX-512, it's just still a work in progress. AVX-512 is enormous (IIRC ~ 4k functions), so it will be a while before it is fully supported. If you're targeting AVX-512 but don't have hardware that supports AVX-512 (like all AMD CPUs), SIMDe can be quite nice. The result is much faster than Intel's SDE and it's just native code that you can use your normal debugger on.