3 ms·
I haven’t been at Intel in ~8 years, but your description of the implementation of x86 is nothing like the processors I worked on. Admittedly, I never worked on
by thechao 6y ago
I haven’t been at Intel in ~8 years, but your description of the implementation of x86 is nothing like the processors I worked on. Admittedly, I never worked on the Xeons; but I would be surprised if decode were 12 watts on those platforms. My guess is that’s off by an easy 2 orders of magnitude.
- jeswin 6y agoMy information is second-hand (I am a software guy); so feel free to correct me here for the benefit of other readers. But here's a study which arrives at a number between 3-10%: https://www.usenix.org/system/files/conference/cooldc16/cooldc16-paper-hirki.pdf https://www.usenix.org/system/files/conference/cooldc16/cool...
- thechao 6y agoYep, looks about right. That benchmark is designed to maximize the decoder cost of the CPU, while effectively idling the rest of the CPU. On some of the architectures I worked on, with the thermals turned off, you could decap the part with decode. But you could also do that by jamming the x87 unit, issuing L0 prefetch, etc. The same is true on the ARM parts I work on. In practice, though, user code doesn’t do this. I’d be interested to see this when the larger L$ are lit—they stop at L2. Also, mops aren’t “RISC”; they’re mops. The only part of the x86 parts I worked in that used a decode ISA was the network & DMA, which desugared down to x86i.