Out of my ass I think three things. One issue is gate loading. Connecting a large number of registers to a bus limits the max throughput. I remember some RISC

Out of my ass I think three things. One issue is gate loading. Connecting a large number of registers to a bus limits the max throughput. I remember some RISC processor they flubbed that. The second is the 68000 had two ALU's one for data and the other for addresses. So can do address and data calculations in parallel. Third separation means you need fewer bits to encode the register addresses in the instruction word.