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We were taught on the newer Coldfire processors which use a modified m68k instruction set. I never understood the reason for the split address and data registe
by filereaper 6y ago
We were taught on the newer Coldfire processors which use a modified m68k instruction set.
I never understood the reason for the split address and data registers, it also seemed like the address registers had a few bits intended for segmentation?
Anyone know the rationale behind the split address vs data registers design and architecture? Most other instruction sets use the same registers for both data and addressing, what advantage do specialized address registers give.
- Gibbon1 6y agoOut of my ass I think three things. One issue is gate loading. Connecting a large number of registers to a bus limits the max throughput. I remember some RISC processor they flubbed that. The second is the 68000 had two ALU's one for data and the other for addresses. So can do address and data calculations in parallel. Third separation means you need fewer bits to encode the register addresses in the instruction word.
- noone_youknow 6y agoI think Gibbon1 has hit the nail in the head in reply to this - it makes the instruction encoding smaller. It also allows the registers to be treated differently on-chip. Combined, this makes stuff like the register indirect with offset addressing modes on 68k both small and fast.
- dboreham 6y agoTwo ALUs?
- jejones3141 6y agoYup. The Signetics 68070 that was used in CD-i was like a 68000, but slower because it didn't have that second ALU.