You see that in, say, Cortex-A76, which only supports AArch32 at EL0. Supporting AArch32 at EL0 is quite cheap compared to also supporting it at the higher exc

You see that in, say, Cortex-A76, which only supports AArch32 at EL0. Supporting AArch32 at EL0 is quite cheap compared to also supporting it at the higher exception levels - EL0 can be done entirely in the instruction decoder.