IANA hardware/cpu guy but, instructions that get decoded get cached in a parallel-to-data-L1 cache, the L1-instruction cache. > Maaaaybe the resultant bandwidt

IANA hardware/cpu guy but, instructions that get decoded get cached in a parallel-to-data-L1 cache, the L1-instruction cache. > Maaaaybe the resultant bandwidth reduction in reading isntructions is worth the performance overhead of x64 instruction decoding. Access to main mem is slow, much slower than decoding circuitry, so it is very well worth it. From what I've read, the decoding time mattered early on, hence (among other reasons) RISC, but as chips speeded up decoding time became less important, then an overhead as the instructions were large. IIRC, and I can't back this up so take with caution, the alpha chips suffered because of this (but of course you could always take large instructions then decode them smaller and cache those decoded instrs). Just my view. Ask a chip expert for a better opinion.