And you do the same in VHDL and Verilog. And like in Chisel, you have to manually pipeline it and you can exactly control where registers are used and how resou

And you do the same in VHDL and Verilog. And like in Chisel, you have to manually pipeline it and you can exactly control where registers are used and how resources are reused. You could build something HLS like using Scala/JVM and Chisel, but Chisel itself is much closer to traditional HDLs. https://en.m.wikipedia.org/wiki/High-level_synthesis https://en.m.wikipedia.org/wiki/High-level_synthesis