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Parts of VHDL leave a little to be desired but overall I find it to be a really great language. To the extent I bought Ada 2012 by John Barnes and I kind of lik

Parts of VHDL leave a little to be desired but overall I find it to be a really great language. To the extent I bought Ada 2012 by John Barnes and I kind of like that too after coding in C/C++ etc, but maybe I'm now biased after many years of VHDL coding :) It's not uncommon to see "VHDL is bad" and such like, and I do wonder what the reasons are for those comments.

exmadscientist 6y ago
As someone who just said that exact thing upthread, half of it is general curmudgeonry. VHDL is not a terrible language, though it does have terrible tools. The IDE side of things is a big opportunity to improve the language. Making refactoring easier by not needing to manually touch up three different files to fix one name is a huge help. (And the IDEs have probably improved in recent times; I've done mostly hardware recently.) The compilers/synthesizers... those are vendor crud and so dragons lie there. VHDL-2008 support would go a long way to improving life....
- froh 6y ago
  If IDE support for basics is an issue,like consistent renaming, then language server protocol support will help: https://github.com/ghdl/ghdl-language-server https://github.com/ghdl/ghdl-language-server Edit: typo in url
adwn 6y ago
> It's not uncommon to see "VHDL is bad" and such like, and I do wonder what the reasons are for those comments. VHDL is bad because it's bad at prototyping and implementing digital hardware [1]. One reason why it's bad at that task is the mismatch between the hardware you want and the way you have to describe it in the language. For example: You want a 32-bit register x which is assigned the value of a plus b whenever c is 0, and you want its reset value to be 25. VHDL code: signal x: unsigned(31 downto 0); ... process (clk, rst) begin if rst then x <= to_unsigned(25, x'length); elsif rising_edge(clk) then if c = '0' then x <= a + b; end if; end if; end; The synthesis software has to interpret the constructs you use according to some quasi-standard conventions, and will hopefully emit those hardware primitives you intended. I say "hopefully", because of the many, many footguns arising from those two translation steps. [1] Okay, I concede that in theory, there might be a use case where VHDL is perfectly suited for, which would make VHDL a not-bad language. But designing digital hardware is not such a use case.
- panpanna 6y ago
  Writing this with good intentions, not trying to start a fight... --- There are some minor issues with your code that shows you are probably a verilog/SV guy and not an experienced VHDL guy. Please read Andrew Rushtons "VHDL for Logic Synthesis". I also recommend you read on VHDLs 9-valued logic and why it was designed this way and how it differs from verilogs Bit.
  - adwn 6y ago
    > you are probably a verilog/SV guy and not an experienced VHDL guy Wrong on both counts. Please, enlighten me, what's wrong with my code? Note that it's in VHDL-2008, and the async. reset is intentional. > I also recommend you read on VHDLs 9-valued logic and why it was designed this way My main issue with VHDL is not the IEEE 1164 std_(u)logic, although it really doesn't help that this de-facto standard type for bitvectors and numbers (via the signed/unsigned types) is just a second-class citizen in the language – as opposed to bit and integer, which are fully supported syntactically and semantically, but which have serious shortcomings.
    - panpanna 6y ago
      Inconsistent Boolean expressions + lack of familiarity with unsigned and how it is supported by the tools. Nothing major, but in my books this is the difference between a Jr and a Sr designer. Nitpicking, yes. But the hardware business is like.
      - adwn 6y ago
        > lack of familiarity with unsigned and how it is supported by the tools Do you mean this: "x <= to_unsigned(25, x'length);" ? Some tools, like Synopsys, allow "x <= 25;" here, but other tools, like ModelSim, do not. The VHDL-2008 standard does not allow "x <= 25;". > Inconsistent Boolean expressions Do you mean because I wrote "if rst ..." but later "if c = '0'..."? Come on, you're not nitpicking, you're trying to find issues where there are none. Fixating on such anal-retentive details does not make you a "Sr designer", it makes you a bad engineer.

exmadscientist 6y ago

As someone who just said that exact thing upthread, half of it is general curmudgeonry. VHDL is not a terrible language, though it does have terrible tools. The IDE side of things is a big opportunity to improve the language. Making refactoring easier by not needing to manually touch up three different files to fix one name is a huge help. (And the IDEs have probably improved in recent times; I've done mostly hardware recently.) The compilers/synthesizers... those are vendor crud and so dragons lie there. VHDL-2008 support would go a long way to improving life....

froh 6y ago
If IDE support for basics is an issue,like consistent renaming, then language server protocol support will help: https://github.com/ghdl/ghdl-language-server https://github.com/ghdl/ghdl-language-server Edit: typo in url

adwn 6y ago

> It's not uncommon to see "VHDL is bad" and such like, and I do wonder what the reasons are for those comments. VHDL is bad because it's bad at prototyping and implementing digital hardware [1]. One reason why it's bad at that task is the mismatch between the hardware you want and the way you have to describe it in the language. For example: You want a 32-bit register x which is assigned the value of a plus b whenever c is 0, and you want its reset value to be 25. VHDL code: signal x: unsigned(31 downto 0); ... process (clk, rst) begin if rst then x <= to_unsigned(25, x'length); elsif rising_edge(clk) then if c = '0' then x <= a + b; end if; end if; end; The synthesis software has to interpret the constructs you use according to some quasi-standard conventions, and will hopefully emit those hardware primitives you intended. I say "hopefully", because of the many, many footguns arising from those two translation steps. [1] Okay, I concede that in theory, there might be a use case where VHDL is perfectly suited for, which would make VHDL a not-bad language. But designing digital hardware is not such a use case.

panpanna 6y ago
Writing this with good intentions, not trying to start a fight... --- There are some minor issues with your code that shows you are probably a verilog/SV guy and not an experienced VHDL guy. Please read Andrew Rushtons "VHDL for Logic Synthesis". I also recommend you read on VHDLs 9-valued logic and why it was designed this way and how it differs from verilogs Bit.
- adwn 6y ago
  > you are probably a verilog/SV guy and not an experienced VHDL guy Wrong on both counts. Please, enlighten me, what's wrong with my code? Note that it's in VHDL-2008, and the async. reset is intentional. > I also recommend you read on VHDLs 9-valued logic and why it was designed this way My main issue with VHDL is not the IEEE 1164 std_(u)logic, although it really doesn't help that this de-facto standard type for bitvectors and numbers (via the signed/unsigned types) is just a second-class citizen in the language – as opposed to bit and integer, which are fully supported syntactically and semantically, but which have serious shortcomings.
  - panpanna 6y ago
    Inconsistent Boolean expressions + lack of familiarity with unsigned and how it is supported by the tools. Nothing major, but in my books this is the difference between a Jr and a Sr designer. Nitpicking, yes. But the hardware business is like.
    - adwn 6y ago
      > lack of familiarity with unsigned and how it is supported by the tools Do you mean this: "x <= to_unsigned(25, x'length);" ? Some tools, like Synopsys, allow "x <= 25;" here, but other tools, like ModelSim, do not. The VHDL-2008 standard does not allow "x <= 25;". > Inconsistent Boolean expressions Do you mean because I wrote "if rst ..." but later "if c = '0'..."? Come on, you're not nitpicking, you're trying to find issues where there are none. Fixating on such anal-retentive details does not make you a "Sr designer", it makes you a bad engineer.