3 ms·
Why not make a Verilog extractor? Then we can simulate it with standard tools. I'm pretty sure Verilog can simulate NMOS since it has pullups. Another option
by jhallenworld 6y ago
Why not make a Verilog extractor? Then we can simulate it with standard tools. I'm pretty sure Verilog can simulate NMOS since it has pullups.
Another option is to extract a Spice netlist.
- duskwuff 6y agoGenerally speaking, Verilog simulation tools don't support the transistor-level primitives. You have to move up to at least the gate level to get something that'll simulate at all; even then, certain special combinations of gates (like registers) have to be specifically recognized to break combinational loops.
- cmrdporcupine 6y agoThis was done for the 6502 from the Visual 6502 netlist, I suspect it could be done from the Z80: http://www.aholme.co.uk/6502/Main.htm http://www.aholme.co.uk/6502/Main.htm But it does look like a lot of work, and it's not like you get especially readable Verilog from it. Given other people have already built cycle accurate cores for these processors that are readable and maintained, it may not be worth it.
- duskwuff 6y agoThe 6502 conversion was especially difficult, as the processor made use of some wacky analog tricks (like capacitive storage) which can't be represented in Verilog at all. The author of that conversion had to do a great deal of manual work to detect these features and convert them to digital logic.