3 ms·

I believe that was software that did the emulation. I actually had a dual Merced system that I ran linux on for a while. It didn’t suck so much as it was “di

I believe that was software that did the emulation. I actually had a dual Merced system that I ran linux on for a while. It didn’t suck so much as it was “different.“ Intel should have known this, but you buy processors because they are faster or cheaper. These days the third rail is energy but it’s basically the same, if you pay more you want a lot more and “Different” costs. Itaniums where a whisker faster than their ia32 offerings at the time, they cost a lot more though, and they were different. Beyond that, it was like a geek designed the specs with out a market story, risc chips were coveted by x86 dorks because they had 32 registers to the x86’s 5 or 6, well ia64 had 128... If you’re just doing simple stack frame compiler work without full program optimization, how many functions need 32 registers? Let alone 128? everyone could see that you wanted to simplify things in order to put silicon where it mattered for longer term performance, mid to late 90s reordering conditionals for branch prediction was sort of hot in compiler dork and low level circles, well Merced fixed that by adding a lot of complex logic to take both branches and retire the wrong one. IBM, HP and Sun needed different reliability and serviceability features on their high end systems too, from the big enterprise metal perspective they were toy parts for PCs, but they cost more, didn’t run your existing software and weren’t 2x faster or anything like that. They didn’t take a holistic market view as they made it. Rather than work with ibm, sun and hp on those high end issues, they just went back to the lab and told them when the first parts would be out. Not really sure what goes on inside intel, they have a lot of brilliant people. I suspect that they cannibalize themselves because nothing will ever be as successful as the x86 was when they owned every aspect of the part and package and things are decided to be a failure before they ship. With ia64 nobody asked why. Xeon phi, they gpu and machine learning stuff reflects that too.

crest 6y ago
You can make use of a lot more than 32 registers, but not with existing RISC or x86 instructions. If I remember correctly EPIC had global registers like your normal RISC, local registers like SPARC and support for batch renaming registers to implement software pipelines. Software pipelining can make use of a lot of registers and exploit the high IPC EPIC was supposed to provide. Still an ISA that avoids the pipeline prologue and epilogue could make software pipelining useful for a lot more algorithms ... in theory.

crest 6y ago

You can make use of a lot more than 32 registers, but not with existing RISC or x86 instructions. If I remember correctly EPIC had global registers like your normal RISC, local registers like SPARC and support for batch renaming registers to implement software pipelines. Software pipelining can make use of a lot of registers and exploit the high IPC EPIC was supposed to provide. Still an ISA that avoids the pipeline prologue and epilogue could make software pipelining useful for a lot more algorithms ... in theory.